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Physical Methods of Speed-Independent Module Design

Написал  в 15 мая 2014, 20:11

Physical Methods of Speed-Independent Module Design
Oleg Izosimov
INTEC Ltd, Room 321, 7a Myagi Street, Samara 443093, Russia
1. Introduction
Any method of logic circuit design is based on using  formal  modelsof gates and wires. The simplest model of a gate is determined by  only  two«parameters»:  (a)  Boolean  function  is  to  be  calculated,   (b)   fixedpropagation delay. The simplest model of a wire  is  an  ideal  medium  withzero resistance and consequently, with zero delay. Such simple models  allowcircuit design procedures which are a sequence of  elementary  steps  easilyrealized by a computer.       When logic circuits designed by using  the  simplest  models  exposeunreliable operation as in the case  of  gate  delay  variations,  designersintroduce less convenient but  more  realistic  models  with  arbitrary  butfinite delay. Using more complicated models may produce logic circuits  thatare called speed-independent .       In speed-independent circuits transition duration can be  arbitrary.So a centralized clock cannot be used. Instead special circuitry  to  detectoutput validity is  applied.  Besides,  additional  interface  circuitry  isneeded to communicate with the environment in a handshaking manner. A speed-independent circuit can be seen as  a  module  consisting  of  combinationallogic  (CL)  proper,  CL  output  validity  detector  (OVD)  and   interfacecircuitry (Fig.1). To enable OVD  to  distinguish  valid  output  data  frominvalid ones, the redundant coding scheme was proposed .  The  main  ideaof the scheme is to enumerate all  possible  input  and  output  data,  bothvalid and invalid. The OVD must be provided with appropriate information  ondata validity. To realize the idea of redundant coding some  constraints  onCL design are imposed :

[pic]
2. Background
Let us have a closer look  at  the  structure  of  speed-independentmodules (SIM) as presented in Fig.1. All input data  are  processed  in  CL,all output data are obtained from CL, too. So, CL is the only  unit  in  SIMwhich is involved in proper data processing. The result of  that  processingis specified by Boolean functions. Algorithms for  calculating  the  Booleanfunction are realised by  the  internal  structure  of  CL.  Generally,  itsstructure is series-parallel as well as algorithm implemented.       When n-bit  data  word  is  put  into  the  CL,  n  or  more  signalpropagation paths (SPPs) can be activated  concurrently.  So,  one  can  saythat the calculation of a Boolean function by CL is of parallel  nature.  Onthe other hand, each SPP is a gate chain which processes data  in  a  serialmanner. So, calculation in CL is also of sequential nature.       The OVD circuit is  intended  for  detecting  transient  and  steady«states» of CL. If any SPP in CL is  still  «active»,  CL  is  in  transientstate, otherwise it is in steady state. Each gate switching results in  bothlogical and electromagnetic effects on its surrounding medium.  The  logicaleffects of switching has been heavily  investigated;  we  consider  physicalone.       To provide speed-independence of the module the  OVD  and  interfacecircuitry must also work in a speed-independent mode. This  means  that  anyarbitrary  but  finite  transistor  or  wire  delay  cannot  impair   properoperation of OVD and interface circuitry.       The interface circuitry is a mediator between OVD and environment ofSIM. It implements any kind of signalling convention,  commonly  a  two-  orfour-cycle one  based on  request  Req  and  acknowledgement  Ack  signalusing. The interface circuitry receives  the  output  validity  (OV)  signalfrom the OVD circuit, a Req signal from the  environment  and  transmits  anAck signal to the environment (Fig.1).       Consider an algorithm of operation for interface circuitry realizingspeed-independent four-cycle signalling  convention  (FCSC).  In  accordancewith FCSC the control signals must go in  the  following  sequence:  Req+OV-Ack+Req-Ack- where «+» corresponds to rising the signal and «-»  correspondsto falling the signal. All signals are assumed to adhere to positive  logic.Initially the signals Req and Ack are low, the signal OV  is  high.  If  theenvironment state changes, the Req signal rises and transient  state  of  CLoccurs (OV-). Upon completion of the transitions in CL, signal OV rises  andthe interface circuitry generates the Ack  signal  rising.  After  that  theenvironment produces a falling Req signal and then the  interface  circuitrytransmits the falling Ack signal to the environment. All  the  signals  haveto be reset into the initial state.       To develop the interface circuitry a circuit designer must take intoaccount that any OVD circuit has finite (non-zero) turn-on delay  ton.  Thismeans that OVD cannot respond on transitions of short duration t tr< ton .       An example of interface circuitry is shown in Fig.2. It  contains  aflip-flop, a NOR-gate, an asymmetrical delay and an inverter  as  an  outputstage .
[pic]
The asymmetrical delay is intended for delaying  Req  rising  signalfor + period where + > ton . Delaying Req falling signal noted —  is  to  beas short as possible. Note that  speed-independent  operation  of  interfacecircuitry is vulnerable to delay + variation. If  + becomes less than ton  ,proper operation of  SIM can not be guaranteed.  Otherwise,  if  +  is  muchmore than ton ,  performance  of  SIM  will  be  significantly  reduced.  Toprovide exact accordance of  + and ton a circuit emulator can be used.       Such an emulator is either an exact copy of OVD  or  its  functionalcopy, i.e. resistive-capacitive model of OVD's critical path.  In  the  chipthe emulator must be placed next to active OVD circuit in  order  to  ensureidentical conditions of fabrication and operation.       In this example we use a simplified asymmetrical  delay  implementedas an asymmetrical CMOS inverter  chain  (Fig.3).  Contrary  to  the  commoninverter an asymmetrical one has non-equal rise and  fall  times  of  outputsignal.                                    [pic]
A time diagram for interface circuitry is presented in Fig.4 for twocases: (a) ttr < ton and (b) ttr  ton.  In  case  (a)  the  signal  sequenceReq+Ack+ is formed for (++tNOR) period where tNOR is a  NOR-gate  delay.  Incase (b) the above sequence is formed for (ttr  +toff+tNOR)  duration  wheretoff is a turn-off delay of  OVD  circuit.  When  the  SIM  returns  to  theinitial steady state, the signal sequence  Req-Ack- is formed  for  (-+tNOR)interval.
[pic]
After considering the SIM in operation it is obvious that  the  mainproblems of the module design are in the area of  CL  and  OVD  interaction.This includes (a) kind of signal used as a carrier of information  about  CLoutput validity, and (b) method of OVD circuit design.
4. Current consumption detection
Using current consumption of CMOS CL for output  validity  detectionwas proposed in 1990 . Contrary to the method of EMR detection  this  oneis based on introducing direct coupling of source and receiver. While CL  isin steady state it consumes current  of  about  10-9-10-8A  which  does  notallow OVD switching. The interface circuitry gets information on  CL  outputvalidity and in turn informs the environment about  CL  readiness  to  inputdata processing. When  an  input  data  arrives  CL  changes  its  state  to«transient», current consumption increases  to  10-4-10-2A,  which  switchesthe OVD, thus informing the interface  circuitry  about  output  invalidity.The latter lets the environment know about CL business.  After the computations in the CL are finished,  the  current  consumptiondecreases down to the steady state value, and the  OVD  sends  a  signal  ofoutput validity.
4.1 Information carrying signal
Current consumption by CMOS CL contains useful   information  on  CLstate. CMOS CL is a network of CMOS gates, so the current consumed by CL  isa superposition of  currents  consumed  by CMOS gates included  in  the  CL.Each CMOS  gate  contains  PMOS  transistor  and  NMOS  transistor  networks(Fig.5). While a gate is in a steady state  either  the  PMOS  or  the  NMOSnetwork is in a conducting mode. When a  gate  switches  the  non-conductingtransistor network becomes conducting. There is usually a  short  period  inswitching time when both networks are in a conducting mode.
[pic]
Generally, current  consumed  by   a   CMOS   gate   includes  threecomponents [9,10]:  (a) leakage current Ilk passing  between  power  supply  and  ground  dueto finite resistance of non-conducting transistor network;  (b) short-circuit current Isc  flowing  while  both  networks  are  in  aconducting mode;  (c) load capacitance CL  charge current ILC  flowing  while  a CMOS  gateis switching from low to high output  voltage  via conducting  PMOS  networkand  CL .       SPICE simulation has shown  that amplitude of current consumed bya typical CMOS inverter depends  on  CL  and  is  limited  by  the  non-zeroresistance of the conducting PMOS network (Fig.7). The integral of  consumedcurrent is proportional to CL . When  a  gate  switches  from  high  to  lowoutput voltage, the component ILC is negative by  direction  and  negligibleby value (Fig.7b). It is evident, the switchings from  high  to  low  outputvoltage occur at  the  expense  of  energy  accumulated  in  CL  during  theprevious switching from low to high output voltage. The component Isc   doesnot depend on direction in which a gate switches.
[pic]                                    [pic]
The component ILC  equals to ILC  = CLVdd f  where Vdd  is  a  powersupply voltage, f is a gate switching frequency. Veendrick has  investigatedthe component Isc dependencies on CL and rise-fall time of  input  potentialsignal . He showed that if both input and output signal  have  the  samerise-fall time, the component Isc cannot be more than 20 percent of  summarycurrent consumption . However, when the output signal rise-fall time  isless than input one,  the  component  Isc  can  be  of  the  same  order  ofmagnitude as ILC. In that case it must be taken  into  account.  As  to  thecomponent Ilk, it entirely depends on CMOS process parameters and for  stateof the art CMOS devices Ilk is about 10-15 -10-12 A.       So, the analysis of CMOS  gate  current  consumption  allows  us  toconclude that  in  transient  state  a  CMOS  gate  consumes  a  current  I=Ilk+Isc+ILC and in steady state it consumes only Ilk<< I  .  The  differencebetween two states from the viewpoint  of  current  consumption  is  severalorders of magnitude. So, CMOS gate output validity  detection  is  possible,both in principle and in practice.       In Section 2 we presented series-parallel model of  computations  inCL. We showed that in every moment during switching current consumed  by  CLis a  superposition  of  the  currents  consumed  on  the  activated  signalpropagation paths (SPPs). Now, considering CL implemented  by  CMOS  deviceswe should  note  that  while  logical  signal  propagates  through  SPP  theneighbouring gates switch in opposite directions. That is  why  a  curve  ofcurrent consumed by a ten inverter chain (Fig.8) looks  like  a  combinationof crests and troughs. Nevertheless, in the very lowest point of  the  curvethe current consumed by CL in a transient state remains several orders  morethan in a steady state.
[pic]
4.2 OVD implementation
The proposed OVD circuit, shown in Fig.9, is  a   threshold  circuittranslating an analog current signal I into a logical signal OV.                                    [pic]       The  OVD  circuit  contains  a  current-to-voltage  converter  (CVC)consisting of the resistor R1 and the diode D1.  The  OVD  also  contains  acomparator implemented by the MOS transistors M1-M7 and resistors R2,,,R3  .CMOS CL consumes the current I  and  introduces  a  capacitance  Cin  .  Thecapacitance Cout represents the load caused by the  interface  circuitry.  Alow potential output signal of OVD corresponds  to  CL  output  validity.  Ahigh potential output signal corresponds to CL output  invalidity.  So,  OVDgenerates OV signal in negative logic manner.       The transfer characteristics of CVC is determined by   a  system  ofthree equations:
[pic] [pic]where I is an input current of CVC, V is a voltage drop on the CVC  circuit,Ir is a current flowing through the resistor R1, Id  is  a  current  passingthrough the diode D1, I0 is a leakage current of the diode,  rb  is  a  bulkresistance of the diode. Here [pic] stands for kT/q where k  is  Boltzmann'sconstant, T is absolute temperature, q is charge of an electron.       Equations (1)-(3) determine  the  functional  connection  F  betweeninput current I and voltage drop V: [pic]. Graphic solution  of  the  systemis shown in Fig.10.                                    [pic]       CVC parameters to be calculated are R1  and  rb.  Initial  data  forcalculating  R1  are  the  threshold  voltage  drop  Vth  and  correspondingthreshold input current Ith . Value Ith is  determined  by  minimal  currentconsumed by CMOS CL in transient state. Initial data for calculating rb  aremaximal voltage drop Vmax and  corresponding  maximal  input  current  Imax.Value Imax is determined by the maximal number  of  gates  in  CL  switchingsimultaneously and their load capacitances.       The comparator chosen is the CMOS ECL receiver proposed by  Chappellet al.. The circuit includes a single differential amplifier stage  withbuilt-in  compensation  for  parameter  variations,  followed  by   a   CMOSinverter.  The  comparator  has  100-mV  worst-case   sensitivity   in   1-mtechnology. Detailed static and dynamic analysis of the  comparator  circuitwas given in .       The comparator compares input  voltage  signal  Vin  with  referencevoltage Vref. If Vin <Vref the comparator  output signal equals  to  logicalzero which means that CL  outputs  are  valid.  Otherwise,  Vin  >Vref,  thecomparator  output  signal equals to logical  «one»  which  means  that  theoutputs are invalid.       As it follows from the OVD circuit configuration,
[pic]     [pic]where Vdd   is a voltage of power supply.       Equations (4) and (5) allow us to calculate the   threshold  voltagedrop V of the CVC circuit:since [pic], so [pic]  [pic]       If 0<V<500mV then the diode D1 of CVC operates  in  the  very  smallcurrent region Id  0 and Id <<Ir. So the  component Id  in the Equation  (1)can be neglected and IIr =V/R1 .       For practical values of [pic]  the threshold input current   of  theOVD circuit is reversely proportional to  the  resistance  of  R1  :  [pic].Substituting Equation (6) yields      [pic].       As to choosing value of rb  it must be done with  regard to  maximalvoltage drop Vmax   .       If V>750mV, the diode D1 is in active mode and  while  rb  <<R1  thecondition Ir <<Id is true. So, in the large current region IId and  Equation(2) determines an almost linear dependence between I and  V.  For  instance,if the maximal voltage drop Vmax =900mV and maximal input current  Imax=2mA,then in accordance  with the Equation (2) rb  100.  Typical  element  valuesfor the OVD circuit with Vth  =400mV are given in Table 1.                                    [pic]
The turn-on ton and turn-off toff delays of the OVD  circuit  dependon the OVD itself and the CMOS CL as well. (Switching the  OVD  output  fromlow to high voltage is called «turning-on» and reverse switching  is  called«turning-off».)       Consider a piece of CMOS CL and its  interaction  with  OVD  circuit(Fig.11). The piece is an SPP including N logic gates. Each  gate  is  shownsymbolically  as  a  connection  of  PMOS  and  NMOS   networks.   All   thecapacitances   affecting   ton  and  toff  can  be  brought  down  to  threecomponents:  (i) CLi   is the load capacitance of the i-th gate;  (ii) Cpsi is the power supply bus capacitance associated  with  the  i-thgate;  (iii) Cin is the input capacitance of the OVD circuit.
[pic]
Let pi is a probability of the i-th gate being in the state of  highoutput potential. In this state the capacitance CLi is connected with  powersupply bus through the low channel resistance of  turned-on  transistors  inPMOS network of the i-th gate. Then equivalent capacitance Ceq connected  tothe OVD circuit input equals
[pic] (7)where N is a number of gates in the considered SPP. Here the  resistance  ofconducting PMOS network is assumed to be negligible.       Equation (7) is also  true  for  CL including  several SPPs. In thatcase summing must be carried out for  all  the gates belonging to CL.       Simulation shows that ton and toff are proportional to the OVD  timeconstant =R1Ceq. It was also obtained that when N>20,  the  component  underthe sign of  summation  in  Equation  (7)  can  be  much  larger  than   thecomponent Cin. Due to voltage drop V the effective power supply  voltage  isreduced and CL performance is decreased by  about  35 percent .       In order to make SIM operating faster special attention must be paidto reducing the capacitance introduced by CL.
[pic]       The main drawback of the circuit is  speed  dependence. One can  seethat  if  true  and  complementary  address  bit   signal   have   differentpropagation delays, the conducting path via NMOS transistors will  never  beformed.       Using the OVD circuit proposed in Section 4.2 as LTD  we  can  avoidthis drawback.        Note  that  address  transmission  through  the  address   bus   isunidirectional. So to detect completion of bus transition  it is  enough  torecognize the bus state at the destination end. For this purpose  we  modifyCL to consist of n lines. The modification means introducing  n  LTDs,  eachactually a CMOS inverter chain. Each chain  contains  two  inverters  loadedwith  a  capacitance  (Fig.13).  Input  of  each  LTD  is   connected   withcorresponding line of the bus at the destination end. Power supply  pads  ofall LTDs are connected to the current input of the same OVD circuit.                                    [pic]       The parameters of the input current signal for the OVD  circuit  arevaried by  (i) value of capacitances C1  and C2 ;  (ii) dimensions of MOS transistors M1 -M4 .       Since all transitions in CL are of the  same  duration  and  can  belengthened to  be  outlast  the  OVD   turning-on  time,   we  simplify  theinterface circuitry by disallowing the  asymmetrical delay.     Due to short duration of normal transition in  this  CL  we  must  takeinto account the integral nature of the sensitivity of the OVD circuit.  OVDsensitivity depends on both amplitude and  width  of  input  current  pulse.Simulated operation region of the OVD circuit  for  current  pulses  shorterthan 30ns is shown in Fig.14. It is obvious that in this case the  thresholdof the OVD circuit must be determined by threshold  charge  Qth  value.  TheOVD input charge Q equals to [pic] where I is OVD  input  current,  t  is  amoment of time when transition occurs,  w  is  a  width  of   input  currentpulse. Turning-on condition for the OVD circuit is Q=Qth.
[pic]       When the LTD circuit shown in Fig.13 is used, the charge value Q  isdetermined by either C1 or C2. Namely, if the line goes  from  low  to  highvoltage, Q=VC2. If the line goes in the reverse direction then  [pic]  whereV is charging/discharging voltage,  approximately  equal  to  the  effectivepower supply voltage: VVdd -V. Here Vdd is OVD power supply  voltage  and  Vis CVC voltage drop.       The OVD  circuit  with  typical  parameters  (See  Table  1)  has  athreshold charge value Qth =4.010-12 C. When C1 =C2 =CL , the minimal  valueof CL providing OVD capacity for operation is about 1.010-12 F.       Influence of transistors M1  -M4   dimensions  on  LTD  delay  d  isdetermined by approximation :
[pic]  where ~ is a sign of proportionality, Gn and Gp are the  conductances  ofNMOS and PMOS transistors respectively (CL =C1 =C2.)        Since [pic] and [pic] where  W  and  L  are  width  and  length  oftransistor channels of the corresponding  conduction type, the LTD  delay  dis  proportional to [pic].       It has been obtained that for [pic], [pic], CL=1.0pF and  Vdd-V=5.0Vthe LTD delay d=7.6ns.       When LTD works jointly with the OVD  in  the speed-independent  bus,the real value of the LTD delay will  increase  by   30-40  percent  due  toOVD's R1 effect  on  the effective  power  supply voltage.       To determine the appropriate value of R1 in the OVD circuit we  mustknow threshold input current Ith corresponding  to  threshold  voltage  dropVth recommended to be equal to 400mV.       Average input  current  Iav  in  transient  state  of  one  line  isdetermined by the expression  Iav =CLv  where  v  is  the  average  rate  ofincrease in the output signal for an inverter included in LTD.  For  typicalvalues v=1.0109 Volts per second and CL =1.0pF, Iav  =1.0mA.  Accepting  Ith=0.4mA and Imax=2.0mA we obtain R1=1k and rb=100.       Simulation has shown that in this case OVD turning-on delay  can  beapproximated by an empirical expression:      ton[ns]=8.1+0.1nwhere n is the address bus bit capacity. Total delay of recognizing  addresstransition ttot =dg+ton where g is a coefficient of the LTD  delay  increasedue to reducing power supply voltage. As we showed above g1.35.  It  can  beseen that if n=32, ttot=21.6ns.
The circuit we use in this Section as a CL  was  a  touch-stone  formany speed-independent circuit designers for about four decades. We  mean  aripple carry adder (RCA) which is actually a chain of  one-bit  full  adders(Fig.14).                                    [pic]       Each full adder calculates two Boolean functions: sum si=aibici  andoutput carry ci+1=aibi+bici+aici  where ai, bi  are summands,  ci  is  inputcarry and  stands for XOR operation.       In 1955 Gilchrist et al. proposed speed-independent RCA  with  carrycompletion signal . In 1960s that circuit  was  carefully  analyzed  andimproved [19-21]. In 1980 Seitz used RCA for  illustrating  his  concept  ofequipotential region and his approach to self-timed system design .       Now we use RCA as a CL for illustrating our approach to SIM design.       As it was shown in Section 4.2 the turn-on and  turn-off  delays  ofthe  OVD  circuit  are  proportional  to  the  equivalent  capacitance   Ceqassociated with OVD circuit input. Capacitance Ceq  depends  linearly  on  anumber of gates N in CMOS CL. To speed up a SIM it is necessary to reduce  anumber N. This can be reached  by  structural  decomposition  CMOS  CL  intosubcircuits CL1, CL2, etc. Each subcircuit  CLi  is  connected  to  its  owndetecting circuit OVDi or directly to the power supply  if  this  subcircuittransition does not affect the transition duration in CL as  a  whole.  Eachdetecting circuit OVDi generates its own OV signal which  is  combined  withother OVDs' output signals via a multi-input OR (NOR)  element.  The  outputsignal of that element serves as OV signal of the CMOS CL.       Multi-bit RCA computation time is determined by  length  of  maximalactivated carry chain. A lot of papers were devoted  to  analysis  of  carrygeneration and carry propagation in RCA  [19-21],  many  of  them  containedtheir  own  methods  for  estimation  or  calculation  of  average   maximalactivated carry chain. We do not intend to add another one.       Let us have a look  inside  RCA.  As  it  was  mentioned  above  RCAconsists of one-bit full adders  and   each   full  adder  consists  of  twoparts: forming sum si part and forming carry ci+1 part (Fig.16).       In multi-bit RCA all forming sum parts do not   interact  with  eachother and do not affect on transition duration  in RCA. Each  forming  carryci+1 part receives ci signal from preceding forming  carry  part  and  sendsci+1 signal to consequent one.       To decompose RCA we use three heuristic tricks:  (i) All forming sum parts we connect directly to power supply.  (ii) We divide each forming carry part into three subcircuits denoted  inFig.16 by numbers 1,2 and  3.  All  subcircuits 1  we  connect  directly  topower supply because they  do not contain input ci and  so  do  not  containcarry propagation path.  (iii) All subcircuits 2 we connect to OVD1 and   all   subcircuits  3  weconnect to OVD2. Outputs of  OVD1  and  OVD2   are  connected  to  two-inputNOR-gate forming  RCA  OV  signal  in positive logic manner (Fig.17).       OVD1 and OVD2 input currents I1 and I2  curves  for  6-bit  RCA  andlongest transition duration are shown in Fig.18.       Accepting Vth1,2=400mV we calculated the OVD circuits parameters. Itwas obtained R11=5k, Ith1=0.08mA, R12=3k, Ith2=0.13mA. OVD1 and  OVD2  delaydependencies on a number of bits in RCA are shown  in  Fig.19.
4.5 Comparison of SIMs with synchronous counterparts
Transition duration in CL is a  random   variable.   Probability  oftransition with duration D is determined  by  implemented  Boolean  functionand distribution of input logical combinations. Domain  of  possible  valuesfor variable  D occupies the interval [0;Dmax]. Here Dmax  is  a  length  ofcritical path in CL.       Let [pic] is a mathematical expectation of transition duration in CLwhere Di is a length of i-th SPP in  CL, pi is a probability  of  i-th  pathbeing the longest activated SPP.       When CL works in the synchronous mode,  the  cycle  duration  Ts  ischosen with regard to maximal transition duration Dmax. Certain margin  mustbe added to Dmax to provide reliable operation of  CL  in  the  case  of  CLparameter variations: Ts =kDmax  where k is a margin coefficient.       In SIM cycle duration is a random variable with  expectation  Tsi  =gDme+toff+tif  where g is a  coefficient  of  CL  delay  increasing  due  toreducing power supply voltage, toff is turn-off delay of  the  OVD  circuit,tif is an interface circuitry delay.       We determine efficiency E for speed-independent mode of CL operationas relative increase of SIM performance in  comparison  to  its  synchronouscounterpart:[pic].       Generally, speed-independent mode is more efficient than synchronousone if Ts >Tsi or, in other words, [pic].       In the case of RCA [pic] where tc is a delay of carry forming  part,n is a number of full adders in RCA.       It has been shown  that in n-bit RCA  Dme tclog2(5n/4). Then, inthe case of speed-independent operation Tsi=gtclog2(5n/4)+toff+tif.       We have obtained dependencies of  Ts , Tsi on a number  of  bits  inRCA that are shown in  Fig.20.  As   it   can   be  seen,  speed-independentoperation of RCA  is  more efficient while n>8.
5.Conclusion
6.Acknowledgement
I would like to thank Igor  Shagurin  and  Vlad  Tsylyov  of  the  MoscowPhysical Engineering Institute for helpful discussions of this  work.  I  amalso grateful to Chris Jesshope of University of Surrey and Mark Josephs  ofOxford University who kindly provided the latest material on their  researchin the area of delay-insensitive circuit design.
References
   Miller,  R.E.,  Switching  theory  (Wiley,  New   York,   1965),vol.2, Chapter 10.           Unger,  S.H.,  Asynchronous  Sequential   Switching   Circuits(Wiley, New York, 1969).         Armstrong, D.B.,  A.D.  Friedman,  and  P.R.  Menon,  Design  ofAsynchronous Circuits Assuming               Unbounded Gate   Delays,   IEEETrans.on Computers C-18 (12) (1969) 1110-1120.         Seitz, C.L., System timing,  in:  C.A.  Mead  and  L.A.  Conway,eds., Introduction   to   VLSI   Systems              (Addison-Wesley,   NewYork, 1980), Chapter 7.         Izosimov,  O.A.,  I.I.  Shagurin,  and  V.V.  Tsylyov,  Physicalapproach to CMOS module self-timing,         Electronics  Letters   26  (22)(1990) 1835-1836.         Veendrick, H.J.M., Short-circuit  dissipation  of   static  CMOScircuit and its impact on  the   design              of   buffer   circuits,IEEE J. Solid-State Circuits SC-19  (4)  (1984)  468-473.         Chappell, B.A, T.I. Chappell, S.E.  Schuster,  H.M.   Segmuller,J.W.  Allan,  R.L.  Franch,  and  P.J.             Restle,  Fast   CMOS  ECLreceivers  with  100-mV  worst-case   sensitivity,   IEEE   J.   Solid-State      Circuits SC-23 (1) (1988) 59-67.         Chu, S.T.,  J.  Dikken,  C.D.   Hartgring,   F.J.   List,   J.G.Raemaekers, S.A. Bell, B. Walsh, and              R.H.W.  Salters,  A  25-nsLow-Power  Full-CMOS  1-Mbit   (128K8)    SRAM,    IEEE    J.    Solid-StateCircuits SC-23 (5) (1988) 1078-1084.         Frank, E.H., and R.F. Sproull, A Self-Timed   Static   RAM,  in:Proc.  Third  Caltech    VLSI                Conference    (Springer-Verlag,Berlin, 1983) pp.275-285.        Donoghue, W.J., and G.E. Noufer, Circuit for address  transitiondetection, US Patent 4563599,                1986.        Huang, J.S.T., and J.W. Schrankler,  Switching   characteristicsof scaled  CMOS  circuits  at  77K,               IEEE  Trans.  on  ElectronDevices ED-34 (1) (1987) 101-106.        Gilchrist, B., J.H. Pomerene, and S.Y. Wong,  Fast  Carry  Logicfor Digital Computers, IRE Trans.            on  Electronic  Computers  EC-4(4) (1955) 133-136.          Hendrickson,  H.C.,   Fast   High-Accuracy   Binary   ParallelAddition, IRE Trans. on Electronic                Computers EC-9 (4)  (1960)465-469.        Majerski, S., and M. Wiweger, NOR-Gate Binary Adder  with  CarryCompletion Detection, IEEE        Trans.  on   Electronic   Computers  EC-16(1) (1967) 90-92.         Reitwiesner,  G.W.,  The  determination  of  carry  propagationlength for binary addition, IRE Trans.            on  Electronic   ComputersEC-9 (1) (1960) 35-38.AppendixSPICE2G.6: MOSFET model parameters
|  |      |                             |      |                   | ||  |      |                             |      |VALUE              | ||  |Name  |Parameter                    |Units |PMOS     |NMOS     ||1 |level |model index                  |-     |3        |3        ||2 |VTO   |ZERO-BIAS THRESHOLD VOLTAGE  |V     |-1.337   |1.161    ||3 |KP    |TRANSCONDUCTANCE             |      |         |         ||  |      |PARAMETER                    |A/V2  |2.310-5  |4.610-5  ||4 |GAMMA |BULK THRESHOLD PARAMETER     |[pic] |0.501    |0.354    ||5 |PHI   |SURFACE POTENTIAL            |V     |0.695    |0.660    ||6 |RD    |DRAIN OHMIC RESISTANCE       |OHM   |333      |85       ||7 |RS    |SOURCE OHMIC RESISTANCE      |OHM   |333      |85       ||8 |CBD   |ZERO-BIAS B-D JUNCTION       |      |         |         ||  |      |CAPACITANCE                  |F     |1.9810-14|6.910-15 ||9 |CBS   |ZERO-BIAS B-S JUNCTION       |      |         |         ||  |      |CAPACITANCE                  |F     |1.9810-14|6.910-15 ||10|IS    |BULK JUNCTION SATURATION     |      |         |         ||  |      |CURRENT                      |A     |3.4710-15|9.2210-15||11|PB    |BULK JUNCTION POTENTIAL      |V     |0.8      |0.8      ||12|CGSO  |GATE-SOURCE OVERLAP CAPACI-  |      |         |         ||  |      |TANCE PER METER CHANNEL WIDTH|F/M   |6.7010-10|3.3010-10||13|CGDO  |GATE-DRAIN OVERLAP CAPACI-   |      |         |         ||  |      |TANCE PER METER CHANNEL WIDTH|F/M   |6.7010-10|3.3010-10||14|CGBO  |GATE-BULK OVERLAP CAPACITANCE|      |         |         ||  |      |                             |F/M   |1.9010-9 |2.6010-9 ||  |      |PER METER CHANNEL LENGTH     |      |         |         ||15|RSH   |DRAIN AND SOURCE DIFFUSION   |      |         |         ||  |      |SHEET RESISTANCE             |OHM/SQ|55       |30       ||16|CJ    |ZERO-BIAS BULK JUNCTION      |      |         |         ||  |      |BOTTOM                       |      |         |         ||  |      |CAPACITANCE PER SQ METER OF  |F/M2  |3.5310-4 |1.2410-4 ||  |      |JUNCTION AREA                |      |         |         ||17|MJ    |BULK JUNCTION BOTTOM GRADING |      |         |         ||  |      |COEFFICIENT                  |-     |0.5      |0.5      ||18|CJSW  |ZERO-BIAS BULK JUNCTION SIDE-|      |         |         ||  |      |                             |      |         |         ||  |      |WALL CAPACITANCE PER METER OF|F/M   |1.7110-10|3.2010-11||  |      |                             |      |         |         ||  |      |JUNCTION PERIMETER           |      |         |         ||  |      |                             |      |         |         |

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